This invention relates to programming integrated circuits, and more particularly, to high speed loading of configuration data files to integrated circuits such as programmable logic devices.
Programmable logic devices are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design tools to design a custom logic circuit. When the design process is complete, the tools generate configuration data files. The configuration data is loaded into memory elements on the programmable logic devices to configure the devices to perform the desired custom logic function.
Programmable logic device memory elements are often based on random-access-memory (RAM) cells. Because the RAM cells are loaded with configuration data during device programming, the RAM cells are sometimes referred to as configuration memory or configuration random-access-memory cells (CRAM).
During normal operation of a programmable logic device, loaded CRAM cells produce static output signals that are applied to the gates of metal-oxide-semiconductor (MOS) field-effect transistors (e.g., pass transistors). The CRAM output signals turn some transistors on and turn other transistors off. This selective activation of certain transistors on the device customizes the operation of the device so that the device performs its intended function.
Prior to use, programmable logic devices are generally tested. During testing, programmable logic resources and interconnects are checked for defects. Such testing takes time and is normally performed by specialized equipment at the programmable logic device manufacturer. If a defect is found, the programmable logic device may be repaired or discarded as appropriate.
Thorough testing of resources on a programmable logic device can be time-consuming. The testing process involves repeated loading of test configuration data files into the programmable logic device to be tested. Each resulting logic configuration may then be tested.
In a typical programmable logic device testing scenario, each test configuration data file may include millions of bits of programming data. Because hundreds of programmable logic device configurations may need to be tested, large quantities of programming data must be loaded into the programmable logic device over the course of the testing procedure.
Loading of configuration data is also required during the normal operation of the device by the end user. It is desirable that the loading time of the configuration data be as short as possible for quick system bring-up.
Existing systems for loading configuration data into programmable logic devices either load the data in a serial single-ended-signal fashion, which tends to be slow, or in a parallel fashion, which may consume an undesirable number of input-output pins.
It would therefore be desirable to provide a system and a method for loading integrated circuits, such as programmable logic devices, in a high speed manner while maintaining minimal integrated circuit pin consumption.